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Integrated Circuit Systems, Inc.
ICS950812
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application: Pin Configuration CK-408 clock with Buffered/Unbuffered mode supporting VDDREF 1 56 REF Almador, Brookdale, ODEM, and Montara-G chipsets with X1 2 55 FS1 PIII/P4 processor. Programmable for group to group skew. X2 3 54 FS0 Output Features: GND 4 53 CPU_STOP#* PCICLK_F0 5 52 CPUCLKT0 * 3 Differential CPU Clock Pairs @ 3.3V PCICLK_F1 6 51 CPUCLKC0 * 7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks PCICLK_F2 7 50 VDDCPU * 3 PCI_F (3.3V) @ 33.3MHz VDDPCI 8 49 CPUCLKT1 GND 9 48 CPUCLKC1 * 1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz PCICLK0 10 47 GND * 1 REF (3.3V) @ 14.318MHz **E_PCICLK1/PCICLK1 11 46 VDDCPU * 5 3V66 (3.3V) @ 66.6MHz PCICLK2 12 45 CPUCLKT2 **E_PCICLK3/PCICLK3 13 44 CPUCLKC2 * 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz VDDPCI 14 43 MULTSEL* * 3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN or 66.6MHz GND 15 42 IREF PCICLK4 16 41 GND Features: PCICLK5 17 40 FS2 * Provides standard frequencies and additional 5% PCICLK6 18 39 48MHz_USB/FS3** and 10% over-clocked frequencies VDD3V66 19 38 48MHz_DOT * Supports spread spectrum modulation: GND 20 37 VDD48 No spread, Center Spread (0.35%, 0.5%, 66MHZ_OUT0/3V66_2 21 36 GND or 0.75%), or Down Spread (-0.5%, -1.0%, or -1.5%) 66MHZ_OUT1/3V66_3 22 35 3V66_1/VCH_CLK/FS4** 66MHZ_OUT2/3V66_4 23 34 PCI_STOP#* * Offers adjustable PCI early clock via latch inputs 66MHZ_IN/3V66_5 24 33 3V66_0/FS5** 2 * Selectable 1X or 2X strength for REF via I C interface *PD# 25 32 VDD3V66 VDDA 26 31 GND * Efficient power management scheme through PD#, GND 27 30 SCLK CPU_STOP# and PCI_STOP#. Vtt_PWRGD# 28 29 SDATA * Uses external 14.318MHz crystal * Stop clocks and functional control available through 56-Pin 300mil SSOP I2C interface. 6.10 mm. Body, 0.50 mm. pitch TSSOP Key Specifications: * These inputs have 120K internal pull-up resistors to VDD. * CPU Output Jitter <150ps ** Internal pull-down resistors to ground. * 3V66 Output Jitter <250ps Note: * 66MHz Output Jitter (Additive) (Buffered Mode) <100ps Almador board level designs MUST use pin 22, * CPU Output Skew <100ps 66MHZ_OUT1, as the feedback connection from the clock buffer path to the Almador (GMCH) chipset.
PLL2 48MHz_USB 48MHz_DOT X1 X2 XTAL OSC
Block Diagram
Frequency Select
Bit FS2 FS1 FS0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 CPUCLK MHz 66.66 100.00 200.00 133.33 66.66 100.00 200.00 133.33 3V66 MHz 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66MHz_OU T (2:0) 3V66 (4:2) MHz 66.66 66.66 66.66 66.66 66MHz_IN 66MHz_IN 66MHz_IN 66MHz_IN 66MHz_IN 3V66_5 MHz 66.66 66.66 66.66 66.66 Input Input Input Input PCICLK_F PCICLK MHz 33.33 33.33 33.33 33.33 66MHz_IN/2 66MHz_IN/2 66MHz_IN/2 66MHz_IN/2
3V66_5/66MHz_IN 3V66_3/66MHz_OUT1 3V66_(4,2)/66MHz_OUT(2,0)
PLL1 Spread Spectrum PD# CPU_STOP# PCI_STOP# MULTSEL FS (5:0) SDATA SCLK VTT_PWRGD#
REF
CPU DIVDER Stop
3 3
CPUCLKT (2:0) CPUCLKC (2:0) PCICLK (6:4, 2, 0)
PCI DIVDER
Stop
7
Control Logic
3V66 DIVDER
2
E_PCICLK(1,3)/PCICLK(1,3) (2:0)
3 PCICLK_F
3V66_0 Config. Reg. 3V66_1/VCH_CLK I REF
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ICS950812
ICS950812
Pin Configuration
PIN # PIN NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 **E_PCICLK1/PCICLK1 PCICLK2 **E_PCICLK3/PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 VDD3V66 GND 66MHZ_OUT0/3V66_2 66MHZ_OUT1/3V66_3 66MHZ_OUT2/3V66_4 66MHZ_IN/3V66_5 PIN TYPE PWR IN OUT PWR OUT OUT OUT PWR PWR OUT I/O OUT I/O PWR PWR OUT OUT OUT PWR PWR OUT OUT OUT I/O DESCRIPTION Ref, XTAL power supply, nominal 3.3V Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. Early/Normal PCI clock output latched at power up. PCI clock output. Early/Normal PCI clock output latched at power up. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. Power pin for the 3V66 clocks. Ground pin. 3.3V 66.66MHz clock output selected via buffered or internal VCO. 3.3V 66.66MHz clock output selected via buffered or internal VCO. 3.3V 66.66MHz clock output selected via buffered or internal VCO. 3.3V 66.66MHz clock from internal VCO, 66MHZ input to 66MHz output and PCI. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 1.8ms. 3.3V power for the PLL core. Ground pin. This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input.
25 26 27 28
*PD# VDDA GND Vtt_PWRGD#
IN PWR PWR IN
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Pin Configuration (Continued)
PIN # PIN NAME 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 SDATA SCLK GND VDD3V66 3V66_0/FS5** PCI_STOP#* 3V66_1/VCH_CLK/FS4** GND VDD48 48MHz_DOT 48MHz_USB/FS3** FS2 GND IREF MULTSEL* CPUCLKC2 CPUCLKT2 VDDCPU GND CPUCLKC1 CPUCLKT1 VDDCPU CPUCLKC0 CPUCLKT0 CPU_STOP#* FS0 FS1 REF PIN TYPE I/O IN PWR PWR I/O IN I/O PWR PWR OUT I/O IN PWR OUT IN OUT OUT PWR PWR OUT OUT PWR OUT OUT IN IN IN OUT DESCRIPTION Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant Ground pin. Power pin for the 3V66 clocks. Frequency select latch input pin / 3.3V 66.66MHz clock output. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low Frequency select latch input pin / 3.3V 66.66MHz clock output / 48MHz VCH clock output. Ground pin. Power pin for the 48MHz output.3.3V 48MHz clock output. Frequency select latch input pin / 3.3V 48MHz clock output. Frequency select pin. Ground pin. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 3.3V LVTTL input for selection the current multiplier for CPU outputs Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Ground pin. Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Stops all CPUCLK besides the free running clocks Frequency select pin. Frequency select pin. 14.318 MHz reference clock.
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Frequency Select Table 1
Freq Sel FS(5:3) FS FS FS 2 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 3V66 MHz 66MHz_OU T (2:0) 3V66 (4:2) 66.66 100.00 200.00 133.33 66.66 100.00 200.00 133.33 70.00 105.00 Tristate 140.00 70.00 105.00 Tristate 140.00 73.32 110.00 Test/2 146.60 73.32 110.00 Test/2 146.60 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 70.00 70.00 Tristate 70.00 70.00 70.00 Tristate 70.00 73.32 73.32 Test/4 73.32 73.32 73.32 Test/4 73.32 66.66 66.66 66.66 66.66 66MHz_IN 66MHz_IN 66MHz_IN 66MHz_IN 70.00 70.00 Tristate 70.00 66MHz_IN 66MHz_IN Tristate 66MHz_IN 73.32 73.32 Test/4 73.32 66MHz_IN 66MHz_IN Test/4 66MHz_IN 66MHz_IN PCI MHz 3V66 _5 66.66 66.66 66.66 66.66 Input Input Input Input 70.00 70.00 Tristate 70.00 Input Input Tristate Input 73.32 73.32 Test/4 73.32 Input Input Test/4 Input 33.33 33.33 33.33 33.33 66MHz_IN/2 66MHz_IN/2 66MHz_IN/2 66MHz_IN/2 35.00 35.00 Tristate 35.00 66MHz_IN/2 66MHz_IN/2 Tristate 66MHz_IN/2 36.66 36.66 Test/8 36.66 66MHz_IN/2 66MHz_IN/2 Test/8 66MHz_IN/2 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 Tristate 14.318 14.318 14.318 Tristate 14.318 14.318 14.318 Test 14.318 14.318 14.318 Test 14.318 REF MHz USB/DOT MHz 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 Tristate 48.008 48.008 48.008 Tristate 48.008 48.008 48.008 Test/2 48.008 48.008 48.008 Test/2 48.008 Clocking Mode
From 000 to 101 (See table 2)
Standard Clocking
Standard Clocking
5% Overclocking Tristate 5% Overclocking Tristate 5% Overclocking 10% Overclocking Test 10% Overclocking Test 10% Overclocking
110 (See table 2)
111 (See table 2)
Frequency Select Table 2
Freq Sel FS FS FS 5 4 3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CPU, 3V66, 66MHz_OUT, 66MHz_IN, PCI Standard Clocking Standard Clocking Standard Clocking Standard Clocking Standard Clocking Standard Clocking 5% Overclocking 10% Overclocking Clocking Mode No Spread (default) or +/-0.4% 0 to -0.5%, Down Spread 0 to -1.0%, Down Spread 0 to -1.5%, Down Spread +/-0.5%, Center Spread +/-0.75%, Center Spread +/-0.35%, Center Spread +/-0.35%, Center Spread
Note: To enable spread, Byte 0 Bit 7 must be set to 1.
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Maximum Allowed Current
Condition Powerdown Mode (PD# = 0) Active Full Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND 40mA 280mA
Host Swing Select Functions
MULTSEL Board Target Trace/Term Z Reference R, Iref = VDD/3*Rr Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA Output Current Voh @ Z
0 1
50 ohms 50 ohms
Ioh = 4 * I REF Ioh = 6 * I REF
1.0V @ 50 ohm 0.7V @ 50 ohm
PCI Select Functions
E_PCICLK1 (11) 0 0 1 1 Note: E_PCICLK1 = 10Kohm resistor. E_PCICLK3 = 10Kohm resistor. 0 = No resistor 1 = 10Kohm pull-up to VDD. * Approximate values E_PCICLK3 (13) 0 1 0 1 E_PCICLK(3,1) 0ns 0.5ns 1.0ns 1.5ns
*
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ICS950812
BYTE 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Pin # 35 53 34
Affected Pin Name Spread Enabled CPUCLKT(2:0) 3V66_1/VCH_CLK/FS4** CPU_STOP#* PCI_STOP#*
Control Function Spread Spectrum Control Power down mode output level 0= CPU driven in power down 1= undriven VCH/66.66 Select Reflects value of pin Reflects value of pin at power up. Also can be set. Frequency Selection Frequency Selection Frequency Selection
Type RW RW RW R RW RW R R
Bit Control 0 1 OFF ON HIGH 66.66 Stop Stop LOW 48.00 Active Active -
PWD 0 0 0 X X X X X
Bit 2 39 FS3 Bit 1 55 FS1 Bit 0 54 FS0 Note: For PCI_STOP# function, refer to table 3.
BYTE 1 Bit 7
Reflects value of pin CPU_Stop mode output level Bit 6 CPUCLKT(2:0) 0= CPU driven when stopped 1 = undriven CPUCLKT2, CPUCLKC2 Allow control of output with Bit 5 45, 44 (see note) assertion of CPU_STOP#. CPUCLKT1, CPUCLKC1 Allow control of output with Bit 4 49, 48 (see note) assertion of CPU_STOP#. CPUCLKT0, CPUCLKC0 Allow control of output with Bit 3 52, 51 (see note) assertion of CPU_STOP#. Bit 2 45, 44 CPUCLKT2, CPUCLKC2 Output control Bit 1 49, 48 CPUCLKT1, CPUCLKC1 Output control Bit 0 52, 51 CPUCLKT0, CPUCLKC0 Output control Note: CPUCLK(2:0) can be turned on/off by CPU_STOP#. Refer to table 4.
Affected Pin Control Function Name REF 1X or 2X Strength control PCICLK6 Output control PCICLK5 Output control PCICLK4 Output control **E_PCICLK3/PCICLK3 Output control PCICLK2 Output control **E_PCICLK1/PCICLK1 Output control PCICLK0 Output control can be turned on/off by PCI_STOP#. Refer to table 3.
Affected Pin Pin # 38 39 Name 48MHz_DOT 48MHz_USB/FS3**
Pin # 43
Affected Pin Name MULTSEL*
Control Function
Type R RW RW RW RW RW RW RW
Bit Control 0 1 HIGH Not Freerun Not Freerun Not Freerun Disable Disable Disable LOW Freerun Freerun Freerun Enable Enable Enable
PWD x 0 0 0 0 1 1 1
BYTE 2 Pin # Bit 7 56 Bit 6 18 Bit 5 17 Bit 4 16 Bit 3 13 Bit 2 12 Bit 1 11 Bit 0 10 Note: PCICLK(6:0)
BYTE 3 Bit 7 Bit 6
Type RW RW RW RW RW RW RW RW
Bit Control 0 1 1X 2X Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable
PWD 0 1 1 1 1 1 1 1
Control Function
Type RW RW RW RW RW RW RW RW
Bit Control 0 Disable Disable Freerun Freerun Freerun Disable Disable Disable 1 Enable Enable Not Freerun Not Freerun Not Freerun Enable Enable Enable PWD 1 1 0 0 0 1 1 1
Output control Output control Allow control of output with Bit 5 7 PCICLK_F2 (see note) assertion of PCI_STOP#. Allow control of output with Bit 4 6 PCICLK_F1 (see note) assertion of PCI_STOP#. Allow control of output with Bit 3 5 PCICLK_F0 (see note) assertion of PCI_STOP#. Bit 2 7 PCICLK_F2 Output control Bit 1 6 PCICLK_F1 Output control Bit 0 5 PCICLK_F0 Output control Note: PCICLK_F(2:0) can be turned on/off by PCI_STOP#. Refer to table 5.
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ICS950812
BYTE 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BYTE 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # 35 33 33 35 24 23 22 21
Affected Pin Name FS4 FS5 3V66_0/FS5** 3V66_1/VCH_CLK/FS4** 66MHZ_IN/3V66_5 66MHZ_OUT2/3V66_4 66MHZ_OUT1/3V66_3 66MHZ_OUT0/3V66_2
Affected Pin Name 3V66(5:2)/66MHZ_OUT(2:0) (See table 6) 3V66(1:0) (See table 7) 48MHz_DOT Slew Control 48MHz_USB Slew Control
Control Function Frequency Selection Frequency Selection Output control Output control Output control Output control Output control Output control
Control Function Unused Reserved Allow control of output with assertion of CPU_STOP#. Allow control of output with assertion of CPU_STOP#. 00 = Medium (default), 01 = Low, 11,10 =High 00 = Medium (default), 01 = Low, 11,10 =High
Type RW RW RW RW RW RW RW RW
Type X X X RW RW RW RW
Bit Control 0 1 Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable
Bit Control 0 1 Not Freerun Freerun Not Freerun Freerun -
PWD X X 1 1 1 1 1 1
Pin # X X X X 38 39
PWD 0 0 0 0 0 0 0 0
Note: Functions in Byte 5 of CK408 were intended as a test and debug byte only.
BYTE 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BYTE 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # X X X X X X X X
Affected Pin Name Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0
Affected Pin Name -
Control Function Revision ID Value Based on Device Revision (Reserved) (Reserved) (Reserved) (Reserved)
Control Function Unused Unused Unused Unused Unused Unused Unused Unused
Type R R R R R R R R
Type R R R R R R R R
Bit Control 0 1 Bit Control 0 1 -
PWD X X X X 0 0 0 1
Pin # X X X X X X X X
PWD 0 0 0 0 0 0 0 0
BYTE 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Pin # X X X X X X X
Affected Pin Name -
Control Function (Reserved) (Reserved) (Reserved) (Reserved)
Type X X X X R R R
Readback Byte Count
Bit Control 0 1 -
PWD 0 0 0 0 1 1 1
Bit 0 X R 1 Note: Byte 8 is for ICS test only. Do not write as system damage may occur. Bit(3:0) contain the readback Byte count.
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ICS950812
BYTE 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # 35 7, 6, 5 13, 12, 11, 10
111 8, 7, 6, 1 1 1, 1 3, 2, 1 0
Affected Pin Name VCHCLK Slew Control PCICLK_F (2:0) Slew Contol PCICLK (3:0) Slew Contol PCICLK (6:0) Slew Contol
Control Function 00 = High(default), 01 = Low, 11,10 = Medium 00 (default), 11 = Medium 01 = Low, 10 =High 00 (default), 11 = Medium 10 = Low, 01 =High 00 (default), 11 = Medium 10 = Low, 01 =High
Type RW RW RW RW RW RW RW RW
Bit Control 0 1 -
PWD 0 0 0 0 0 0 0 0
BYTE 10 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # X X 24, 23, 22, 21 33, 35 X X
Affected Pin Name 3V66(5:2)/66MHZ_OUT(2:0) Skew 3V66(1:0) Skew -
Control Function M/N Enable (Enable access to Byte 11 - 14) Unused Approx 250ps per bit (Ref to PCI) Approx 250ps per bit (Ref to PCI) Unused Unused
Type RW RW RW RW RW -
Bit Control 0 1 Byte HW/B0 (11-14) -
PWD 0 0 0 0 0 0 0 0
BYTE Affected Pin Bit Control Control Function Type Pin # Name 0 1 11 Bit 7 X VCO Divider Bit8 RW Bit 6 X REF Divider Bit6 RW Bit 5 X REF Divider Bit5 RW Bit 4 X REF Divider Bit4 RW Bit 3 X REF Divider Bit3 RW Bit 2 X REF Divider Bit2 RW Bit 1 X REF Divider Bit1 RW Bit 0 X REF Divider Bit0 RW Note: The decimal representation of these 7 bits (Byte 11 bit[6:0]) + 2 is equal to the REF divider value. Note: See table 8 for Byte 11-14 default information
BYTE 12 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Affected Pin Name Control Function VCO VCO VCO VCO VCO VCO VCO VCO Divider Divider Divider Divider Divider Divider Divider Divider Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Type RW RW RW RW RW RW RW RW Bit Control 0 1 -
PWD X X X X X X X X
Pin # X X X X X X X X
PWD X X X X X X X X
Note: The decimal representation of these 9 bits (Byte 12 bit[7:0]) and Byte 11 bit [7]) + 8 is equal to the VCO divider value.
Note: See table 8 for Byte 11-14 default information
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ICS950812
BYTE 13 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # X X X X X X X X
Affected Pin Name -
Control Function Spread Spectrum Bit7 Spread Spectrum Bit6 Spread Spectrum Bit5 Spread Spectrum Bit4 Spread Spectrum Bit3 Spread Spectrum Bit2 Spread Spectrum Bit1 Spread Spectrum Bit0
Type RW RW RW RW RW RW RW RW
Bit Control 0 1 -
PWD X X X X X X X X
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Note: See table 8 for Byte 11-14 default information
BYTE 14 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Affected Pin Name Bit Control 0 1 -
Pin # X X X X X X X X
Control Function (Reserved) (Reserved) Spread Spectrum Bit13 Spread Spectrum Bit12 Spread Spectrum Bit11 Spread Spectrum Bit10 Spread Spectrum Bit9 Spread Spectrum Bit8
Type RW RW RW RW RW RW RW RW
PWD X X X X X X X X
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Note: See table 8 for Byte 11-14 default information
Spread Spectrum Enable Procedure Step 1: Power-up ---- Latched inputs, FS(5:0), set frequency per Hardware default on board. SS is off. BIOS program set IIC Byte0, bit7 to 1, SS will be enable Spread. Note that Byte 10, bit 7 is default to 0. This allows all setup to be controlled by the Frequency Select Tables, 1 and 2. Step 2: After power up, SS% can be changed to the fixed selections shown in Frequency Table 2. This is achieved by Writing to Byte 4, bit 6/7 (FS5:4) and/or Byte 0 (FS3), The data written to these bytes will overwrite the existing contents and switch to the desired selection. Step 3: To set up Linear programming and SS% adjust using Byte 11 through 14, the BIOS must set Byte 10, bit 7 to a 1. This will enable access to Byte 11 and 12, M/N linear programming and Byte 13 and 14, Spread Spectrum % adjust.
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Table 3 PCI_STOP# I2C Control Table-Byte 0, Bit 3
PCI_STOP# (Pin 34) Byte 0 Bit 3 Write Bit Byte 0, Bit 3 Read Bit (Internal Status)
0 0 0 0 1 0 1 0 0 1 1 1 Note: When this Byte 0, Bit 3 is low (0), all PCI clocks are stopped.
Table 4 CPUCLKT/C (2:0) Outputs I2C Control Table
Byte 1 CPU_STOP# CPUCLKT/C (2:0) Outputs Bit 3, 4, 5 (Pin 53) 0 0 Stop 0 1 Running 1 0 Running 1 1 Running Note: Individual CPUCLK outputs are controlled by Byte 1, Bit 3, 4, and 5.
Table 5 PCICLK_F (2:0) Outputs I2C Control Table
PCI_STOP# Byte 3 PCICLK (2:0) Outputs Bit 3, 4, 5 (Pin 34) 0 0 Stop 0 1 Running 1 0 Running 1 1 Running Note: Individual PCICLK outputs are controlled by Byte 3, Bit 3, 4, and 5.
Table 6 3V66 (5:2)/66MHz_OUT(2:0)/66MHz_IN I2C Control Table
CPU_STOP# (Pin 53) Byte 5 Bit 5 3V66 (5:2) (Driven) 66MHZ_OUT(2:0)/66MHZ_IN (Buffered)
0 0 Running 0 1 Stopped 1 0 Running 1 1 Running Note: Activating Byte 5, Bit 5 will allow CPU_STOP# to control stop of pins 21, 22, 23, and 24.
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Table 7 3V66 (0:1) I2C Control Table
CPU_STOP# Byte 5 3V66 (1:0) (Pin 53) Bit 4 0 0 Running 0 1 Stopped 1 0 Running 1 1 Running Note: Activating Byte 5, Bit 4 will allow CPU_STOP# to control stop of pins 33 and 35.
Table 8: Byte 11-14 Defaults
ADDRESS
FS5 FS4 FS3 FS1 FS0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CPU Freq 66.66 99.99 199.98 133.32 66.50 99.75 199.50 133.00 66.34 99.51 199.02 132.68 66.16 99.23 198.47 132.31 66.66 99.99 199.98 133.32 66.66 99.99 199.98 133.32 70.00 105.00 210.00 140.00 73.33 109.99 219.98 146.65
Spread Center Down Center Center Center Center Down Down Down Down Down Down Down Down Down Down Down Down Center Center Center Center Center Center Center Center Center Center Center Center Center Center Center Center 11 0.40% 0.40% 0.40% 0.40% -0.48% -0.48% -0.48% -0.48% -0.98% -0.98% -0.98% -0.98% -1.52% -1.52% -1.52% -1.52% 0.51% 0.51% 0.51% 0.51% 0.74% 0.74% 0.74% 0.74% 0.35% 0.35% 0.35% 0.35% 0.34% 0.34% 0.34% 0.34% 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 90 90 90 90 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 89 89 89 89
Bytes I2C read back values in Hex. 12 9B 9B 9B 9B 9A 9A 9A 9A 99 99 99 99 EB EB EB EB 9B 9B 9B 9B 9B 9B 9B 9B B0 B0 B0 B0 4A 4A 4A 4A 13 02 02 02 02 EF EF EF EF E7 E7 E7 E7 DD DD DD DD 05 05 05 05 0B 0B 0B 0B 35 35 35 35 68 68 68 68 14 18 18 18 18 17 17 17 17 17 17 17 17 17 17 17 17 18 18 18 18 18 18 18 18 19 19 19 19 1A 1A 1A 1A 11 10001101 10001101 10001101 10001101 10001101 10001101 10001101 10001101 10001101 10001101 10001101 10001101 10010000 10010000 10010000 10010000 10001101 10001101 10001101 10001101 10001101 10001101 10001101 10001101 10001101 10001101 10001101 10001101 10001001 10001001 10001001 10001001 I2C read back values in binary. 12 10011011 10011011 10011011 10011011 10011010 10011010 10011010 10011010 10011001 10011001 10011001 10011001 11101011 11101011 11101011 11101011 10011011 10011011 10011011 10011011 10011011 10011011 10011011 10011011 10110000 10110000 10110000 10110000 01001010 01001010 01001010 01001010 13 00000010 00000010 00000010 00000010 11101111 11101111 11101111 11101111 11100111 11100111 11100111 11100111 11011101 11011101 11011101 11011101 00000101 00000101 00000101 00000101 00001011 00001011 00001011 00001011 00110101 00110101 00110101 00110101 01101000 01101000 01101000 01101000 14 00011000 00011000 00011000 00011000 00010111 00010111 00010111 00010111 00010111 00010111 00010111 00010111 00010111 00010111 00010111 00010111 00011000 00011000 00011000 00011000 00011000 00011000 00011000 00011000 00011001 00011001 00011001 00011001 00011010 00011010 00011010 00011010
0542G--08/21/03
11
ICS950812
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +90C Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 90C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage SYMBOL V IH VIL IIH Input High Current IIH IIL1 Input Low Current IIL2 IDD3.3OP Operating Supply Current IDD3.3OP Powerdown Current Input Frequency Pin Inductance Input Capacitance1 Clk Stabilization1,2 Delay 1
1 2
CONDITIONS
MIN 2 VSS0.3
TYP
MAX VDD+0. 3 0.8 5.75 200
UNITS V V mA A mA A
VIN = VDD; Inputs with no pull-down resistors VIN = VDD; Inputs with pull-down resistors VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = Full load; Select @ 100 MHz CL =Full load; Select @ 133 MHz IREF=5 mA V DD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From PowerUp or deassertion of PowerDown to 1st clock. Output enable delay (all outputs) Output disable delay (all outputs)
-5.75 -200 233 234 20 0.289 14.32 280 280 52 0.5 7 5 6 45 2.1 12 12
mA mA mA mA MHz nH pF pF pF ms ns ns
IDD3.3PD IDD3.3PDHIz Fi Lpin CIN COUT CINX TSTAB tPZH,tPZL tPHZ,tPLZ
27
30 1
1 1
Guaranteed by design, not 100% tested in production. See timing diagrams for buffered and un-buffered timing requirements.
0542G--08/21/03
12
ICS950812
Electrical Characteristics - CPU (1V Select) 100MHz
TA = 0 - 90C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Current Source Output Impedance Average Period Output High Voltage Output Low Voltage Rise Time Fall Time Duty Cycle Skew Jitter, Cycle to cycle
1 2
SYMBOL Zo1 TPERIOD V OH3 V OL3 tr3 tf3 dt3 tsk3 tjcyc-cyc 1
CONDITIONS V O = Vx Fig. 5 Measured from Single Ended Waveform VOL = 0.41V, VOH = 0.86V (Fig. 6) VOH = 0.86V VOL = 0.41V (Fig.6) Fig. 5 VT = 50% VT = 50%
MIN 2500 10.00 0.92 -0.2 175 175 45
TYP
MAX
UNITS
10.01
390 305 51 10 40
10.20 1.45 0.35 540 540 55 100 175
ns V ps ps % ps ps
Guaranteed by design, not 100% tested in production. IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - CPU (0.7V Select) 100MHz
TA = 0 - 90C; VDD=3.3V +/-5%; (unless otherwise specified) PARAMETER Current Source Output Impedance Average Period Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Skew Jitter, Cycle to cycle
1 2
SYMBOL Zo1 TPERIOD VHigh VLow Vovs Vuds Vcross(abs) d-Vcross tr tf d-t r d-t f dt3 t sk3 t jcyc-cyc 1
CONDITIONS VO = V x Fig. 1 Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Fig. 3 Variation of crossing over all edges (Fig. 4) VOL = 0.175V, VOH = 0.525V (Fig. 3) VOH = 0.525V VOL = 0.175V (Fig. 3)
MIN 3000 10.00 660 -150 -450 250 175 175
TYP
MAX
UNITS
Measurement from differential wavefrom (Fig 1) VT = 50% VT = 50% (Fig. 1)
45
10.01 720 15 750 -2 319 12 310 300 10 10 51 16 48
10.20 850 150 1150 550 140 810 810 125 125 55 100 175
ns mV mV mV mV ps ps ps ps % ps ps
Guaranteed by design, not 100% tested in production. IOWT can be varied and is selectable thru the MULTSEL pin.
0542G--08/21/03
13
ICS950812
Electrical Characteristics - CPU (0.7V Select) 133.33MHz
TA = 0 - 90C; VDD=3.3V +/-5%; (unless otherwise specified) PARAMETER Current Source Output Impedance Average Period Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Skew Jitter, Cycle to cycle
1
SYMBOL Zo1 TPERIOD VHigh VLow Vovs Vuds Vcross(abs) d-Vcross tr tf d-tr d-tf dt3 tsk3 tjcyc-cyc
1
CONDITIONS VO = Vx Fig. 1 Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Fig. 3 Variation of crossing over all edges (Fig. 4) VOL = 0.175V, VOH = 0.525V (Fig. 3) VOH = 0.525V VOL = 0.175V (Fig. 3)
MIN 3000 7.50 660 -150 -450 250 175 175
TYP
MAX
UNITS
7.51 718 17 730 7 340 15 310 315 5 5
7.65 850 150 1150 550 140 810 810 125 125 55 100 175
ns mV mV mV mV ps ps ps ps % ps ps
Measurement from differential wavefrom (Fig 1) VT = 50% VT = 50% (Fig. 1)
45
51 14 75
Guaranteed by design, not 100% tested in production. 2 I OWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - PCICLK Buffered Mode
TA = 0 - 90C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter,cycle to cyc
1
SYMBOL RDSP11 V OH1 V OL1 IOH1 IOL1 tr11 tf11 dt11 tsk11 tjcyc-cyc 1
CONDITIONS V O = V DD*(0.5) IOH = -1 mA IOL = 1 mA VOH@MIN = 1.0V, V OH@MAX = 3.135V V OL @MIN = 1.95V, VOL @MAX = 0.4V VOL = 0.4 V, VOH = 2.4 V (Fig. 7) VOH = 2.4 V, VOL = 0.4 V (Fig. 7) V T = 1.5 V V T = 1.5 V V T = 1.5 V (Additive) (Fig. 8)
MIN 12 2.05
TYP 33
MAX 65 0.65
UNITS V V mA mA ns ns % ps ps
-33 26 0.5 0.5 45 1.4 1.2 52 35 60
-28 38 2.3 2.3 55 500 120
Guaranteed by design, not 100% tested in production.
0542G--08/21/03
14
ICS950812
Electrical Characteristics - PCICLK Un-Buffered Mode
TA = 0 - 90C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Impedance Average Period Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter,cycle to cyc
1
SYMBOL RDSP11 TPERIOD VOH1 VOL1 IOH1 IOL1 tr11 tf11 dt11 tsk11 tjcyc-cyc
1
CONDITIONS VO = VDD*(0.5) Fig. 8 IOH = -1 mA IOL = 1 mA VOH@MIN = 1.0V, VOH@MAX = 3.135V V OL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V (Fig. 7) VOH = 2.4 V, VOL = 0.4 V (Fig. 7) V T = 1.5 V (Fig. 8) VT = 1.5 V V T = 1.5 V (Fig. 8)
MIN 12 30.00 2.05 -33 26 0.5 0.5 45
TYP 33 30.01
MAX 65
UNITS ns V
0.65 -28 38 1.4 1.2 50 65 101 2.3 2.3 55 500 290
V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics- 3V66 - Buffered Mode: 3V66 [1:0] 66MHz_OUT [2:0]
TA = 0 - 90C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter Skew Jitter
1
SYMBOL RDSP11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 dt11 tsk11 tjcyc-cyc 1 tsk11 tjcyc-cyc 1 V
CONDITIONS V O = V DD*(0.5) IOH = -1 mA IOL = 1 mA
OH@MIN = 1.0 V, V OH@MAX
MIN 12 2.05
TYP 33
MAX 65 0.65
UNITS V V mA mA ns ns % ps ps ps ps
= 3.135 V
-33 26 0.5 0.5 45 1.6 1 52 10 83 169 83
-28 38 2.3 2.3 55 250 120 250 290
VOL @MIN = 1.95 V, V OL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V (Fig. 7) VOH = 2.4 V, V OL = 0.4 V (Fig. 7) VT = 1.5 V (Fig. 8) VT = 1.5 V 3V66 [1:0]
V T = 1.5 V 3V66 [1:0] (Additive) (Fig. 8) VT = 1.5 V 66MHz_OUT [2:0] VT = 1.5V 66MHz_OUT [2:0] (Fig. 8)
Guaranteed by design, not 100% tested in production.
0542G--08/21/03
15
ICS950812
Electrical Characteristics - 3V66 -Un-Buffered Mode: 3V66 [5:0]
TA = 0 - 90C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Impedance Average Period Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP11 TPERIOD V OH1 VOL1 IOH1 IOL1 tr11 tf11 dt11 tsk11 tjcyc-cyc
1
CONDITIONS VO = VDD*(0.5) Fig. 8 IOH = -1 mA IOL = 1 mA V
OH@MIN
MIN 12 15.00 2.05 = 3.135 V -33 26 0.5 0.5 45
TYP 33 15.01
MAX 65 15.30 0.65 -28 38
UNITS ns V V mA mA ns ns % ps ps
= 1.0 V, V
OH@MAX
V OL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V (Fig. 7) VOH = 2.4 V, VOL = 0.4 V (Fig. 7) V T = 1.5 V (Fig. 8) VT = 1.5 V VT = 1.5 V (Fig. 8)
1.6 1.2 48 40 133
2.3 2.3 55 250 290
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 90C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Fig. 8 Output Frequency FO1 1 VO = VDD*(0.5) Output Impedance RDSP1 1 IOH = -1 mA Output High Voltage VOH Output Low Voltage Output High Current Output Low Current 48DOT Rise Time 48DOT Fall Time VCH 48 USB Rise Time VCH 48 USB Fall Time 48 DOT Duty Cycle VCH 48 USB Duty Cycle 48 DOT Jitter USB to DOT Skew VCH Jitter
1
MIN 20 2.05
TYP 48 48
MAX 70 0.5
UNITS MHz V V mA mA ns ns ns ns % % ps ns ps
V OL
1
IOL = 1 mA V
OH@MIN = 1.0 V, V OH@MAX
IOH1 IOL1 tr11 tf11 tr11 tf11 dt11 dt11 tjcyc-cyc tsk11 tjcyc-cyc
1 1
= 3.135 V
-29 25 0.5 0.5 1 1 45 45 0.7 0.8 1.2 1.4 53 53 183 0.43 157
-20 27 1.15 1.15 2.3 2.3 55 55 410 1 410
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V (Fig. 7) VOH = 2.4 V, VOL = 0.4 V (Fig. 7) VOL = 0.4 V, VOH = 2.4 V (Fig. 7) VOH = 2.4 V, VOL = 0.4 V (Fig. 7) VT = 1.5 V (Fig. 8) VT = 1.5 V (Fig. 8) VT = 1.5 V (Fig. 8) VT = 1.5 V (0 OR 180 degrees) VT = 1.5 V (Fig. 8)
Guaranteed by design, not 100% tested in production.
0542G--08/21/03
16
ICS950812
Electrical Characteristics - REF (1X select)
TA = 0 - 90C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL FO1 RDSP11 V OH1 VOL1 IOH1 IOL1 tr1 tf1
1 1
CONDITIONS Fig. 8 VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V
OH@MIN
MIN 20 2.05
TYP 14.32 48
MAX 70 0.45
UNITS MHz V V mA mA ns ns % ps
= 1.0 V, V
OH@MAX
= 3.135 V
-29 25 1 1 45 1.1 1.4 53 180
-25 27 2.3 2.3 55 1200
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V (Fig. 7) VOH = 2.4 V, VOL = 0.4 V (Fig. 7) VT = 1.5 V
1
dt11 tjcyc-cyc
VT = 1.5 V (Fig. 8)
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF (2X select)
TA = 0 - 90C; VDD=3.3V +/-5%; CL = 20-40 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 dt11 tjcyc-cyc
1
CONDITIONS Fig. 8 VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V
OH@MIN
MIN
TYP 14.32
MAX
UNITS MHz V V
= 1.0 V, V
OH@MAX
= 3.135 V 1 1 45 1.1 0.9 53 180 2.3 2.3 55 1200
mA mA ns ns % ps
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V (Fig. 7) VOH = 2.4 V, VOL = 0.4 V (Fig. 7) VT = 1.5 V VT = 1.5 V (Fig. 8)
Guaranteed by design, not 100% tested in production.
0542G--08/21/03
17
ICS950812
Figure 1 - Differential (CPUCLK - CPUCLK#) Measurement Points (Tperiod, Duty Cycle, Jitter)
TPERIOD
High Duty Cycle %
Low Duty Cycle %
0.000 V
Figure 2 - 0.7V Differential TRise and TFall Measurement Points
CPUCLK#
+0.35V
0.0V
-0.35V
CPUCLK
TRISE
TFALL
0542G--08/21/03
18
ICS950812
Figure 3 - 0.7V Single Ended Measurement Points for TRise, TFall
TRISE (CPUCLK) V
OH
= 0.525
CP
UC
LK
#
U CP
CL
K
VCROSS
V
OL
= 0.175V TFALL (CPUCLK#)
Figure 4 - 0.7V VCross Range Measurement Clarification
VCROSS(REL) max VCROSS(REL) min
Total VCROSS Variation (140mV max)
0542G--08/21/03
19
ICS950812
Figure 5 - 1.0V Single Ended VCross, VOH and VOL Measurement Points
VOH Max 1.45V CPUCLK# VOH Min 0.92V
VCROSS Max 0.76V VCROSS Min 0.51V
VOL Max 0.35V CPUCLK VOL Min -0.20V
Figure 6 - 1.0V Single Ended Measurement Points for TRise, TFall
TRISE (CPUCLK) V
OH
= 0.86V
CP
UC
LK
#
U CP
CL
K
VCROSS
V
OL
= 0.41V TFALL (CPUCLK#)
0542G--08/21/03
20
ICS950812
Figure 7 - Measurement Points for TRise, TFall with Lumped Load
2.4V
1.5V
0.4V
Figure 8 - Measurement Points for TPeriod, Duty Cycle and Jitter
TPERIOD
High Duty Cycle %
Low Duty Cycle %
1.5V
0542G--08/21/03
21
ICS950812
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit Slave Address D2(H) WR WRite T Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P
0542G--08/21/03
Not acknowledge stoP bit
22
ICS950812
Buffered Mode - 3V66[0:1], 66MHz_IN, 66MHz_OUT[0:2] and PCI Phase Relationship All 3V66 clocks are to be in phase with each other. All 66MHz_OUT clocks are to be in phase with each other. There is NO phase relationship between the 3V66 clocks and the 66MHz_OUT and PCI clocks. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1_VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. The 66MHz_IN to 66MHz_OUT delay is shown in the figure below and is specified to be within a min and max propagation value.
66MHz_IN 66MHz_OUT 3V66
Tpd
No Relationship Tpci
PCICLK_F (2:0) PCICLK (6:0)
E_PCICLK (3,1) Tepci
Group to Group Skews at Common Transition Edges: Buffered Mode
GROUP 66MHz_IN 66MHz_OUT1,2 66MHz_OUT to PCI 1,2
1 2
SYMBOL Tpd Tpci
CONDITIONS Propogation delay from 66MHz_IN to 66MHz_OUT (2:0) 66MHz_OUT (2:0) leads 33 MHz PCICLK
MIN 2.5 1.5
TYP 2.9
MAX 4.5 3.5
UNITS ns ns
Guaranteed by design, not 100% tested in production. 500ps Tolerance
E_PCICLK to PCICLK Skews
GROUP SYMBOL TE_PCI-PCI1 E_PCICLK to PCICLK 1 TE_PCI-PCI2 TE_PCI-PCI3
1
CONDITIONS E_PCICLK1 (pin 11)=0 E_PCICLK3 (pin 13)=1 E_PCICLK1 (pin 11)=1 E_PCICLK3 (pin 13)=0 E_PCICLK1 (pin 11)=1 E_PCICLK3 (pin 13)=1
MIN 0.3 0.8 1.3
TYP 0.5 1.0 1.5
MAX 0.7 1.2 1.7
UNITS ns ns ns
Guaranteed by design, not 100% tested in production.
0542G--08/21/03
23
ICS950812
Un-Buffered Mode 3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1_VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci.
3V66 (1:0) 3V66 (4:2) 3V66_5 PCICLK_F (2:0) PCICLK (6:0) E_PCICLK (3,1) Tepci Tpci
Group to Group Skews at Common Transition Edges: Unbuffered Mode
GROUP 3V66 to PCI1,2
1 2
SYMBOL S3V66-PCI
CONDITIONS 3V66 (5:0) leads 33MHz PCI
MIN 1.5
TYP 2.55
MAX 3.5
UNITS ns
Guarenteed by design, not 100% tested in production. 500ps Tolerance
E_PCICLK to PCICLK Skews
GROUP SYMBOL TE_PCI-PCI1 E_PCICLK to PCICLK 1 TE_PCI-PCI2 TE_PCI-PCI3
1
CONDITIONS E_PCICLK1 (pin 11)=0 E_PCICLK3 (pin 13)=1 E_PCICLK1 (pin 11)=1 E_PCICLK3 (pin 13)=0 E_PCICLK1 (pin 11)=1 E_PCICLK3 (pin 13)=1
MIN 0.3 0.8 1.3
TYP 0.5 1.0 1.5
MAX 0.7 1.2 1.7
UNITS ns ns ns
Guaranteed by design, not 100% tested in production.
0542G--08/21/03
24
ICS950812
PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge. Assertion of PCI_STOP# Waveforms
PCI_STOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition. When the I2C Bit 6 of Byte 1 is programmed to '0' the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive current values. The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not be driven . When the I2C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU and CPU# outputs will not be driven. Assertion of CPU_STOP# Waveforms
CPU_STOP# CPUCLKT CPUCLKC
CPU_STOP# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
0542G--08/21/03
25
ICS950812
CPU_STOP# - De-assertion (transition from logic "0" to logic "1") All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the de-assertion to active outputs is to be defined to be between 2 - 6 CPU clock periods (2 clocks are shown). If the I2C Bit 6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 10 nS of CPU_Stop# deassertion.
De-assertion of CPU_STOP# Waveforms
CPU_STOP# CPUCLKT(2:0) Tdrive_CPU_STOP# <10ns @ 200mV *CPUCLKT(2:0)TS CPUCLKC(2:0) *Signal TS is CPUCLKT in Tri-State mode
PD# - Assertion (transition from logic "1" to logic "0") When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks must be held low on their next high to low transitions. When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks must be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz. Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. Power Down Assertion of Waveforms
0ns PD# CPUCLKT 100MHz CPUCLKC 100MHz 3V66MHz 66MHz_IN 66MHz_OUT PCICLK 33MHz USB 48MHz REF 14.318MHz 25ns 50ns
PD# Functionality
PD# 1 0
0542G--08/21/03
CPUCLKT Normal iref * Mult
CPUCLKC Normal Float
3V66 66MHz Low
66MHz_OUT 66MHz_IN Low
PCICLK_F PCICLK
66MHz_IN/2
PCICLK
66MHz_IN/2
USB/DOT 48MHz 48MHz Low
Low
Low
26
ICS950812
Power Down De-Assertion Mode The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping of the power supply until the time that stable clocks are output from the clock chip. If the I2C Bit 6 of Byte 0 is programmed to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.
Test Configuration Diagrams
Rs=33 Ohms 1% TLA Rdif=475 Ohms 1% Rs=33 Ohms 1% TLB
CLK408
CPUCLKT test point
Rp=63.4 Ohms 1%
Rp=63.4 Ohms 1% 2pF 5% 2pF 5%
CPUCLKC test point
RREF=221 Ohms 1%
MULTSEL Pin must be Low
CPU 1.0V Configuration test load board termination
Rs=33 Ohms 5% TLA
CLK408
Rs=33 Ohms 5% TLB
CPUCLKT test point
Rp=49.9 Ohms 1% Rset=475 Ohms 1%
Rp=49.9 Ohms 1% 2pF 5% 2pF 5%
CPUCLKC test point
MULTSEL Pin must be High
CPU 0.7V Configuration test load board termination
0542G--08/21/03
27
ICS950812
N
c
L
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A 2.41 2.80 A1 0.20 0.40 b 0.20 0.34 c 0.13 0.25 SEE VARIATIONS D E 10.03 10.68 E1 7.40 7.60 0.635 BASIC e h 0.38 0.64 L 0.50 1.02 SEE VARIATIONS N 0 8 VARIATIONS N 56 D mm. MIN 18.31 MAX 18.55
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
D (inch) MIN .720 MAX .730
Reference Doc.: JEDEC Publicat ion 95, M O-118
300 mil SSOP Package
10-0034
Ordering Information
ICS950812yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging Lead Free (optional) Package Type F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0542G--08/21/03
28
ICS950812
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 56
10-0039
-Ce
b SEATING PLANE
aaa C
D mm. MIN MAX 13.90 14.10
D (inch) MIN .547 MAX .555
Reference Doc.: JEDEC Publicat ion 95, M O-153
6.10 mm. Body, 0.50 mm. pitch TSSOP (20 mil) (240 mil)
Ordering Information
ICS950812yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging Lead Free (optional) Package Type G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0542G--08/21/03
29

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